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Title: Circuits and Systems for Lab on Chip and Lab on CMOS Systems
Speaker: Pamela Abshire
Affiliation: University of Maryland
10:00-10:45 / October 12 / Room España 2
Circuits and Systems for Lab on Chip and Lab on CMOS Systems
Lab-on-a-chip (LOC) systems are miniaturized devices that integrate several laboratory functions onto a single “chip”. These “chips” are usually passive substrates, which require most LOC systems to be used in conjunction with benchtop equipment for sensing and control. By integrating active electronics into traditional passive LOC systems, a new class of highly integrated multiphysics lab-on-CMOS (LoCMOS) systems has emerged that places instrumentation in intimate contact with sensing and actuation capabilities. The integration of active integrated circuits with signal processing, detection, and actuation increases complexity of integration but reduces the need for external instrumentation, leading to overall systems with significantly smaller size and also the potential for completely novel measurements that cannot be performed using traditional approaches.
This talk will provide an overview of circuits and systems for LoC and LoCMOS systems and the technologies used to construct them. It will introduce emerging sensors for monitoring the characteristics of cultured biological cells. The integration of diagnostic sensors into LoCMOS devices poses a number of distinct and vexing challenges, including packaging, surface fouling, sterilization, communication, and system power. We will focus on sensors and technology integration for two LoCMOS applications: 1) a nose-on-a-chip that detects the spiking activity of olfactory sensory neurons; and 2) surface attachment sensors that measure the viability of cancer cells and in vivo response to chemotherapeutic agents. In each of these applications, we have demonstrated the ability to monitor the activity of individual cultured cells. This class of devices has the potential to introduce significant and disruptive changes in healthcare diagnosis and delivery in the near future.
Pamela Abshire is a Professor in the Department of Electrical and Computer Engineering and the Institute for Systems Research at the University of Maryland, College Park. She received the BS in physics with honor from the California Institute of Technology in 1992, and the MS and PhD in electrical and computer engineering from The Johns Hopkins University in 1997 and 2002, respectively. Her main areas of expertise are in low power mixed-signal integrated circuits and CMOS biosensors. Her research advances integrated circuits that are informed by biology – taking inspiration from the organizational principles found in biological systems or providing for direct interface with biological systems. This includes biosensors, laboratory on CMOS systems, sensor interface circuits, adaptive VLSI circuits, information power efficiency, and hybrid systems incorporating CMOS, MEMS, optoelectronics, microfluidics, and biological components. She has developed sensors and signal processing circuitry for a variety of applications, including bioelectronic olfactory sensing, high performance imaging, cell viability sensors, and adaptive data conversion. Selected honors include an NSF CAREER award (2003) and elevation to IEEE Fellow for contributions to CMOS biosensors (2018). She previously served on the Emerging Technologies and Research Advisory Committee for the U.S. Department of Commerce, on the Board of Governors for the IEEE Circuits and Systems Society, and as General Co-Chair for the 2017 IEEE International Symposium on Circuits and Systems. In 2019 she served on the IEEE Fellow Committee, the IEEE Ethics and Member Conduct Committee, and the IEEE Conference Publications Committee. She currently serves on the Microsystems Exploratory Council for the DARPA Microsystem Technology Office and as General Co-Chair for the IEEE Midwest Symposium on Circuits and Systems (MWSCAS) 2023.
Title: VLSI Architectures for Reed-Solomon Codes: Classic, Nested, Coupled, and Beyond
Speaker: Xinmiao Zhang
Affiliation: The Ohio State University
10:00-10:45 / October 12 / Room España 3
VLSI Architectures for Reed-Solomon Codes: Classic, Nested, Coupled, and Beyond
Reed-Solomon (RS) codes and their binary BCH subcodes have been traditionally used for error correction in numerous digital communication and storage systems, such as optical communications, deep-space probing, Flash memories, and magnetic storage. Variations of RS/BCH codes are also the best candidates for many emerging systems. Through nesting RS/BCH codes, the recently-developed generalized integrated interleaved (GII) codes can meet the terabit/s throughput and excellent error-correcting capability requirements of next-generation communications and storage. Besides, the new coupled and split-parity RS codes achieve low-latency/local failure recovery and accordingly enable the continued scaling of hyper-scale distributed storage and computing. This talk first reviews state-of-the-art VLSI implementation architectures for classic error-correcting RS and BCH decoders. Then the challenges and recent advancements on the implementation of the GII codes are discussed. The third part will focus on erasure-correcting decoding of the variations of RS codes for efficient failure recovery in distributed storage.
Xinmiao Zhang received her Ph.D. degree from the University of Minnesota. She joined The Ohio State University as an Associate Professor in 2017. She was previously a Timothy E. and Allison L. Schroeder Associate Professor at Case Western Reserve University. Between her academic positions, she was a Senior Technologist at Western Digital/SanDisk Corporation. Her research focuses on VLSI architecture design, digital storage and communications, security, and signal processing. Dr. Zhang received an NSF CAREER Award in 2009. She authored the book “VLSI Architectures for Modern Error-Correcting Codes” and published 90 papers on related topics. She was elected to serve on the Board of Governors 2019-2021 and is a member of the VSA and CASCOM TCs of IEEE CASS. She is also a Vice-Chair of the Data Storage TC of the IEEE Communications Society 2017-2020. She served on the committees of many conferences, including ISCAS, SiPS, ICC, GLOBECOM, GlobalSIP, and GLSVLSI.
Title: CloudFPGA - A Scalable Reconfigurable Computing Platform
Speaker: Christoph Hagleitner
Affiliation: IBM Research - Zurich Research Laboratory
10:00-10:45 / October 12 / Room España 4
CloudFPGA - A Scalable Reconfigurable Computing Platform
The long success story of Moore's law and technology scaling is slowly approaching its limits and the whole industry is looking for hardware accelerators, which can continue to advance performance and energy efficiency. At the same time, cloud computing is evolving into the dominant computing platform. While GPUs are the dominant accelerators today, an increasing number of companies and universities are exploring the use of reconfigurable computing based on FPGAs. Reconfigurable computing offers the architectural flexibility to accelerate a wide range of workloads in combination with improved power efficiency. These observations led to the development of cloudFPGA, a reconfigurable computing platorm based on network-attached FPGAs. CloudFPGA achieves scalability through a novel packaging concept and disaggregation. In this presentation we are going to describe how the basic components of the platform and how AI inference applications can be deployed and scaled.
Christoph Hagleitner leads the "Heterogeneous Cognitive Computing Systems" group at the IBM Research –Zurich Lab (ZRL) in Ruschlikon, Switzerland. The group focuses on heterogeneous computing systems for cloud datacenters and HPC. Applications include security, big-data analytics and cognitive computing. He obtained a diploma degree in Electrical Engineering from ETH, Zurich, Switzerland in 1997 and a Ph.D. degree for a thesis on CMOS-integrated Microsensors from ETH, Zurich, Switzerland in 2002. In 2003 he joined IBM Research to work on the system architecture of a novel probe-storage device (“millipede”-project). In 2008, he started to build up a new research group in the area of accelerator technologies. The team initially focused on on-chip accelerator cores and gradually expanded its research to heterogeneous systems and their applications.
Title: Design and Development of Neuromodulation Devices
Speaker: Firat Yazicioglu
Affiliation: Galvani Bioelectronics
10:00-10:45 / October 12 / Room España 5
Design and Development of Neuromodulation Devices
There is increasing R&D worldwide on neuromodulation therapies. Various new therapies beyond deep brain and spinal cord stimulation are emerging. These therapies are considered complementary to existing pharmaceutical therapies. Given the highly regulated environment of implantable medical devices, this talk with start with regulatory landscape, discuss methods for developing neuromodulation therapies, and presents translational approaches for studying performance and safety of new technologies. Specifically neural interface and place of electronics in emerging neuromodulation devices will be discussed.
Firat is VP and Head of Research Devices and Technology Development at Galvani Bioelectronics, a joint venture between GSK (GlaxoSmithKline) and Verily (former Google Lifesciences). Working in Neuromodulation Devices, he joined GSK Bioelectronics in 2015 after spending 13 years at imec, Europe’s largest independent research centre in microelectronics and nanoelectronics. He has developed devices and technologies for medical-grade wearable and implantable biomedical devices, including wireless cardiac monitoring patches, wearable EEG monitoring headsets and implantable neural probes for high density recording. Firat was also involved in the creation of a San Francisco-based wearable healthcare start-up, Bloom Technologies.
With a Ph.D. from KU Leuven in Belgium, Firat has authored more than 100 peer-reviewed publications along with 20 patents, including a book on low-power biomedical microsystems. He has served on the technical program committees of European Solid State Circuits Conf (ESSCIRC), International Solid State Circuits Conf (ISSCC), and Biomedical Circuits and Systems Conf (BioCAS) and remains Associate Editor for IEEE Trans. of Biomedical Circuits and Systems..
Title: Power Grids in the Midst of Rapidly Increasing Penetration of Power Electronics
Speaker: Chi K. Tse
Affiliation: City University of Hong Kong
Chi K. Tse
10:00-10:45 / October 12 / Room Andalucía 1-2
Power Grids in the Midst of Rapidly Increasing Penetration of Power Electronics
The penetration of power electronics into power generation and distribution systems has deepened in recent years, as prompted by the increasing use of renewable sources, quest for higher performance in the control of power conversion, as well as the increasing influence of economical plans that necessitate power trading among different regions or clusters of power distribution. As a result of the increased use of power electronics for controlling power flows in power systems, interactions of power electronics systems and conventional synchronous machines' dynamics would inevitably cause stability and robustness concerns, which can be readily understood by the coupling effects among interacting dynamical systems of varying stability margins (or transient performances). In this lecture, we discuss the various problems of power electronics penetration into power grids and the implications on the stability and robustness of power networks.
Chi K. Michael Tse received the BEng degree with first class honors and the PhD degree from the University of Melbourne, Australia. He is presently Chair Professor of Electrical Engineering at City University of Hong Kong. Prior to joining City University in October 2019, he was with the Hong Kong Polytechnic University, where he assumed Head of the Department of Electronic and Information Engineering in 2005-2012 and was a member of the University Council in 2013-2015. His research interests include complex network applications, power electronics and nonlinear systems. He serves and has served as Editor-in-Chief of IEEE Transactions on Circuits and Systems II, IEEE Circuits and Systems Magazine, IEICE Nonlinear Theory and Applications; as Editor of International Journal of Circuit Theory and Applications, and associate editor of a few other IEEE journals. He has been appointed to honorary professorship and distinguished fellowship by a few Australian, Canadian and Chinese universities, including the Chang Jiang Scholar Chair with Huazhong University of Science and Technology, Honorary Professor of Melbourne University, Distinguished International Research Fellow with the University of Calgary, and Distinguished Professor-at-Large with the University of Western Australia. Dr Tse is an IEEE Fellow and an IEAust Fellow.
Title: Challenges and Opportunities of Massive Applications of Artificial Intelligence
Speaker: Shipeng Li
Affiliation: IngDan Labs
10:00-10:45 / October 12 / Room Andalucía 3-4
Challenges and Opportunities of Massive Applications of Artificial Intelligence
In this talk, Dr. Li will first introduce different levels of artificial intelligence from a data perspective and give an honest estimation on the timeframe to reach each level of AI. He will then give an overview of the state-of-the-art AI technologies and some exciting applications enabled by AI using some industrial examples. He will then go ahead to analyze the challenges and opportunities we are facing today for massive applications of AI technologies in real world. He will also point out research directions and solutions to some of the pressing issues we are facing today.
Dr. Shipeng Li is Vice President of Shenzhen Institute of Artificial Intelligence and Robotics for Society (AIRS). He was with a leading AI company in China serving as Corporate Vice President and Co-President of Research. Before that he was CTO of a leading IoT company in China. He was a founding member of Microsoft Research Asia (MSRA). Dr. Li was once a Research Area Manager and Principal Researcher at MSRA, and a Microsoft Partner in 1999-2015. Before Microsoft, Dr. Li was with Sarnoff Corporation as Member of Technical Staff.
Dr. Li is the Editor-in-Chief of IEEE Transactions on Circuits and Systems for Video Technology, a Fellow of IEEE, and IEAS (International Eurasian Academy of Science) Academician. He is an influential expert on multimedia, internet, computer vision, cloud computing, IoT and artificial intelligence, holding 200 US patents and 330+ international technical publications with 21,879+ citations (H-index: 76). He has trained 4 MIT TR35 winners (the world's top 35 innovators under the age of 35) over the years. He serves as a Standing Committee Member of Chinese Institute of Electronics, Co-Founder and Joint Secretary General of Artificial Intelligence Industry Technology Innovation Strategic Alliance under China MOST.
Title: Nonlinear Dynamics and Control of Biological Circuits and Systems
Speaker: Mario di Bernardo
Affiliation: University of Bristol, UK
Mario di Bernardo
10:00-10:45 / October 12 / Room Andalucía 6-7
Nonlinear Dynamics and Control of Biological Circuits and Systems
Synthetic Biology is an emerging field of research whose aim is to endow living cells with new functionalities with applications ranging from healthcare (personalized therapies) to industry and biotechnology (biomaterials, batch fermentation etc). In this talk I will give an overview of recent efforts on developing tools for the modelling, design and feedback control of synthetic circuits and systems in living cells. After giving a broad overview of the area, I will focus on the problem of engineering microbial cellular consortia able to perform a desired function. Challenges in the development (and validation) of microbial consortia include the design of Gene Regulatory Networks (GRNs) that cooperate to achieve a common goal, the maintenance of stable coexistence between different populations, and the development of technologies for the in-vivo validation and prototyping of the proposed designs. During the talk I will use a combination of in-silico mathematical predictions, and in-vivo experimental results to illustrate the key concepts and developments.
Mario di Bernardo (SMIEEE ’06, FIEEE 2012) is Professor of Automatic Control at the University of Naples Federico II, Italy and Professor of Nonlinear Systems and Control (part-time) at the University of Bristol, U.K. On 28th February 2007 he was bestowed the title of Cavaliere of the Order of Merit of the Italian Republic for scientific merits from the President of Italy. He was elevated to the grade of Fellow of the IEEE in January 2012 for his contributions to the analysis, control and applications of nonlinear systems and complex networks. He was Vice President for Financial Activities of the IEEE Circuits and Systems Society and a member of its Board of Governors. He was Distinguished Lecturer of the IEEE Circuits and Systems Society for the two-year term 2016-2017.
Title: Large Area Energy Autonomous Electronic Skin
Speaker: Ravinder Dahiya
Affiliation: University of Glasgow
10:00-10:45 / October 13 / Room España 2
Large Area Energy Autonomous Electronic Skin
Advances in microelectronics over 50 years have revolutionized our lives through fast computing and communication. Recent advances in the field are propelled by applications such as wearable systems, and healthcare technologies, etc. Often these applications require electronic devices and circuits to be soft and Squishy so that they could conform to 3D surfaces. These requirements call for new methods to realize electronic devices and circuits on unconventional substrates such as plastics, papers and elastomers. This overview lecture will present various approaches that are being explored to obtain distributed electronics, sensing and computing on soft and flexible substrates, especially in context with the energy autonomous tactile or electronic skin in robotics. These approaches range from distributed off-the-shelf electronics integrated on flexible printed circuit boards to novel alternatives such as printed nanowires-based electronics and ultra-thin chips, etc. This cross-cutting technology is also the key enabler for numerous emerging fields such as internet of things, smart cities and mobile health, etc.
Ravinder Dahiya is a Professor of Electronics and Nanoengineering at the University of Glasgow. His group (Bendable Electronics and Sensing Technologies (BEST)) conducts fundamental research on high-mobility materials based on flexible electronics leading to electronic skin and their application in robotics and wearable systems.
Prof. Dahiya has published more than 280 research articles, 4 books, and 15 patents submitted/granted. He has given more than 140 invited/plenary talks. He has led many international projects (~ £30M) funded by the European Commission, EPSRC, The Royal Society, The Royal Academy of Engineering, and The Scottish Funding Council.
He is Fellow of IEEE, President-Elect (2020-21) and Distinguished Lecturer of the IEEE Sensors Council. He is serving on the editorial boards of several leading journals. He holds EPSRC Fellowship and received in past the Marie Curie Fellowship and Japanese Monbusho Fellowship. He also received the 2016 IEEE Sensor Council Technical Achievement Award and the 2016 Microelectronic Engineering Young Investigator Award (Elsevier).
Title: High Speed Data Communications over Plastic Optical Fibers
Speaker: Alberto Rodríguez-Pérez
Affiliation: KDPOF S. L., Spain
10:00-10:45 / October 13 / Room España 3
High Speed Data Communications over Plastic Optical Fibers
Plastic Optical Fiber (POF) is an interesting alternative optical communication channel to the Glass Optical Fibers (GOF) for some applications which do not require to cover long distances, such as home or automotive networking. However, the reduced low bandwidth of the POF channel imposes big limitations in the maximum data bitrate that can be transmitted through this medium. Consequently, advanced data communication techniques, such as channel equalization, data error correction or data signal modulation, has to be applied to get data bitrates above 1 Gbps. This lecture shows an overview of the use of Plastic Optical Fiber (POF) as a medium for optical data communications and the techniques needed to get high speed data bitrates over POF.
Alberto Rodríguez-Pérez, received the B.S. degree in telecommunication engineering and the PhD degree in Microelectronics from the University of Seville, Spain, in 2007 and 2013, respectively. During his PhD research, devised at the Institute of Microelectronics of Seville from 2008 to 2012, he completed the design of complete System-on-Chip neural recorder interfaces with embedded data compression that got significant international impact. His Phd work, besides published in prime line journals, was awarded the Extraordinary PhD Award of the University of Sevilla. In 2013, he joined THE R&D department of NXP Semiconductors in Eindhoven, The Netherlands, where he worked on the design of new and efficient topologies for high-speed serial interfaces transceivers for wireline communications. In 2014, he joined KDPOF S.L., a start-up company settled in Madrid, Spain, which produces high-speed optical communication systems. There, he started and leads the Analog & Mixed Signal department, in charge of developing the optoelectronics and the analog front-end for the optical transceivers. He was also an Associate Professor at the University Carlos III of Madrid, Spain from 2015 to 2018. He has authored and co-authored more than 30 papers, 3 book chapters and 8 patent applications. Currently, his main research interests are in the design of high-speed optical and wirelines transceivers, covering advanced modulation and equalization techniques, high-speed ADCs, VCSEL and LED drivers and trans-impedance amplifiers.
Title: Overview on the Emerging Versatile Video Coding Standard
Speaker: Mathias Wien
Affiliation: RWTH Aach University
10:00-10:45 / October 13 / Room España 4
Overview on the Emerging Versatile Video Coding Standard
The talk provides an overview on the latest emerging video coding standard VVC (Versatile Video Coding) to be jointly published by ITU-T and ISO/IEC. VVC is planned to be finalized by July 2020. It has been designed to achieve significantly improved compression capability compared to previous standards such as HEVC, and at the same time to be highly versatile for effective use in a broadened range of applications. Important design criteria for VVC have been low computational complexity on the decoder side and friendliness for parallelization on various algorithmic levels. The talk details the video layer coding tools specified in VVC and provides an overview of its high-level syntax design. Novel design aspects are highlighted and a comparison to its predecessor HEVC is provided.
Mathias Wien works as senior researcher and Privatdozent at Lehrstuhl für Bildverarbeitung, RWTH Aachen University where he leads the Visual Media Communication group. His research interests include image and video processing, immersive, space-frequency adaptive and scalable video compression, and robust video transmission. Mathias has been an active contributor to VVC and previous standards. He has participated and contribute to ITU-T VCEG, ISO/IEC MPEG, the Joint Video Team (JVT), the Joint Collaborative Team on Video Coding (JCT-VC), and the Joint Video Experts Team (JVET) of VCEG and ISO/IEC MPEG. Mathias has published more than 60 scientific articles and conference papers in the area of video coding and has co-authored several patents in this area. Mathias has further authored and co-authored more than 200 standardization documents. He has published the Springer textbook “High Efficiency Video Coding: Coding Tools and Specification”, which fully covers Version 1 of HEVC.
Title: CMOS image sensors for scientific, bio-medical and space applications
Speaker: Renato Turchetta
Affiliation: Imasenic S. L., Spain
10:00-10:45 / October 13 / Room España 5
CMOS image sensors for scientific, bio-medical and space applications
CMOS image sensors are today the technology of choice for imagers in consumer products. Mobile phones have provided the market drive to continuously improving the technology, which finds today more and more usage in other applications as scientific and bio-medical.
The talk will first briefly review the status of the technology for consumer and other high-volume applications, before moving to reviewing CMOS image sensors for some high-end applications, namely scientific, bio-medical and space. Among the topics reviewed is the use of CMOS image sensors for the detection outside the visible range and including X-rays and particles, options for fully depleted sensors and the development of large area sensors (manufactured by stitching techniques), up to the size of a full 200 or 300 mm wafers.
Dr Renato Turchetta received the M.S. degree from the University of Milan (Italy) in 1988 and the Ph.D. from the University of Strasbourg (France) in 1991. In 1999 he joined the Rutherford Appleton Laboratory in the UK, where he founded and led a design group developing custom CMOS image sensors for advanced applications, among which: a 16 million, radiation-hard image sensors for the direct detection of electrons and a global shutter, 5 million frames per second, megapixel image sensor. In 2014 he co-founded Vivamos Ltd., set up to commercialise his 6.7 megapixel, wafer-scale, video rate CMOS image sensors. He was executive director of the company until the end of 2016. He then co-founded IMASENIC S.L., which develops custom CMOS image sensors. He is member of the Advisory Board for the annual Image Sensors Europe conference since 2011. He also authored or co-authored over 100 papers in peer-review journals and 10 patents.
Title: Ultra-Low-Power Circuit Techniques for Power Management and Energy Harvesting ICs
Speaker: Vadim Ivanov
Affiliation: Texas instrument
10:00-10:45 / October 13 / Room Andalucía 1-2
Ultra-Low-Power Circuit Techniques for Power Management and Energy Harvesting ICs
This lecture covers power management of systems having long periods of idle time with very low power consumption alternated by active high power states, like systems with power harvesting. Circuit techniques used in ultra-low power analog circuits applicable in power harvesting systems will be presented, including nanoampere biasing, voltage references with sub-volt supply, active rectifiers, comparators, oscillators and error amplifiers. Also covered design techniques and circuits of DC/DC converters, providing high efficiency at a wide range of loads down to the microampere range and LDOs with dynamic biasing.
MSEE 1980, Ph.D. 1987, both in the USSR. Designed electronic systems and ASICs for naval navigation equipment from 1980 to 1991 in St. Petersburg, Russia and mixed signal ASICs for sensors, GPS/GLONASS receivers and for motor control between 1991 and 1995.
Joined Burr Brown (presently Texas Instruments, Tucson) in 1996, where worked on the operational, instrumentation, power amplifiers, references and switching and linear voltage regulators, and where he is currently the Operational Amplifier Technologist. Has 108 patents, with more pending, on analog circuit techniques and authored > 30 technical papers and three books: “Power Integrated Amplifiers” (Leningrad, Rumb, 1987), “Analog system design using ASICs” (Leningrad, Rumb, 1988), both in Russian, and “Operational Amplifier Speed and Accuracy Improvement”, Springer, 2004. Member of ESSCIRC technical committee.
Title: S4oC: A Self-organizing, Self-adapting Secure System-on-Chip to Tackle Unknown Threats – A Multi-Layer Network Theoretic, Learning Approach
Speaker: Shahin Nazarian
Affiliation: University of Southern California
10:00-10:45 / October 13 / Room Andalucía 6-7
S4oC: A Self-organizing, Self-adapting Secure System-on-Chip to Tackle Unknown Threats – A Multi-Layer Network Theoretic, Learning Approach
We propose a framework for the design and optimization of a hierarchical self-organizing, self-adapting system-on-chip (S4oC) architecture. The goal is to minimize the possibility of attacks, such as hardware Trojan, and side channel, by learning to make real-time adjustments when necessary. S4oC will learn to reconfigure itself, subject to various security measures, and attacks, some of which possibly unknown. Furthermore, the types and data patterns of the multiple applications, environmental conditions, and sources of variations are incorporated. S4oC is a manycore system, modeled as a three-layer graph, representing the model of computation (MoCp), model of communication (MoCm), and model of memory (MoM) with a large number of heterogeneous reconfigurable processing element (PEs) in MoCp, and a large number of memory elements (MEs) in the MoM layer, including multi-level caches. Community detection and learning are utilized for application task clustering and mapping to S4oC to optimize for security.
Shahin Nazarian received his Ph.D. degree in Electrical Engineering from the University of Southern California (USC). He is currently an Associate Professor of Engineering Practice within the ECE Department of USC. His research interests include computer-aided design, verification and optimization of system-on-chip, hardware acceleration, and signal integrity. His industrial experiences, as a consultant, technical expert, and software and hardware design engineer, span over a wide range of areas, including computer software analysis, computer architecture, and embedded systems. He is the Founder and President of Vervecode, Inc., is a consulting company offering design, and analysis services in various software and hardware engineering fields.
Title: Visual Prosthesis for the blind
Speaker: Patrick Degenaar
Affiliation: Newcastle University
10:00-10:45 / October 14 / Room España 2
Visual Prosthesis for the blind
It is an exciting time for Electronic engineers interested in developing implantable electronics. Recognition of the importance in the field can be found in the billions of $/€ being spent in respective brain projects in the EU, US and China. Private sector interest is also flourishing with Neurolink and Galvani being two remarkable companies in recent years. And yet all has not been well in the visual prosthesis field with the two key German/US systems being removed from the market.
This lecture will explore the root causes of blindness for which visual prosthetics is applicable and what can be done to restore vision through neuroprosthetic means. It will then review the technical, regulatory and economic challenges of bringing next generation systems to trials. As the field goes back to basics to solve these problems, this talk will review the fruitful new areas of research and perspectives for the coming decade.
Prof. Patrick Degenaar received a bachelor (first-class) degree in applied physics and an MRes. Degree in surface science from Liverpool University, Liverpool, U.K., in 1996 and 1997, respectively. After a short period In the MedTech industry in Ireland, he went on to complete a Ph.D. in Bioimaging and Bioelectronics the Japan Advanced Institute of Science and Technology in 2001.
In 2002, After some time in the software industry, he joined Imperial College, London as a post-doc. In 2005, he received an RCUK Fellowship and was promoted to a junior lecturer position. He was further promoted to a senior lectureship before departing to join Newcastle University in 2010, where was promoted to a full professor in neuroprosthetics in 2019.
His primary research interests as an academic lie in optogenetics, Neuroprosthetics, and in particular visual prosthetics. Between 2010-2014 Dr Degenaar was the coordinator of the OptoNeuro FP7 project. Since then, he has been the lead engineer on the flagship CANDO project in clinical neuroprosthetics. He has published around 200 peer reviewed papers and has a dozen patents.
Title: Low-Power SAR ADC Techniques and Applications
Speaker: Pieter J. A. Harpe
Affiliation: Eindhoven university of Technology
Pieter J. A. Harpe
10:00-10:45 / October 14 / Room España 3
Low-Power SAR ADC Techniques and Applications
Successive Approximation Register (SAR) ADCs are nowadays widely used for applications that require medium resolution and a sampling rate anywhere from near-DC up to tens of GS/s. This presentation starts with an introduction why and how SAR ADCs have become such a dominant and attractive choice. A few examples will be given of key techniques that improve the efficiency of the comparator and the DAC, two of the most critical blocks in a low-power SAR ADC. The talk will further explain how the favorable features of the SAR ADC, like the dynamic power consumption as well as the small chip area, can be advantageously used inside versatile on-demand sensing applications, or area-constrained applications. Last but not least, the talk will elaborate on limitations, alternatives, and future expectations of the SAR ADC.
Pieter J. A. Harpe received the M.Sc. and Ph.D. degrees from the Eindhoven University of Technology, The Netherlands, in 2004 and 2010, respectively.
After working for several years at Holst Centre/imec, he is currently an Associate Professor on low-power mixed-signal circuits at the Integrated Circuits Group of Eindhoven University of Technology.
Dr. Harpe is co-organizer of the yearly workshop on Advances in Analog Circuit Design (AACD), and is the Analog track chair for the ESSCIRC conference. He also served as International Technical Program Committee member for ISSCC, was an IEEE Solid-State Circuits Society Distinguished Lecturer and is a Senior IEEE member since 2015. He is recipient of the ISSCC 2015 Distinguished Technical Paper Award.
Title: Ultra-Low Power Sensor Systems – The Fuel for Artificial Intelligence
Speaker: Ralf Brederlow
Affiliation: Technical University of Munich
10:00-10:45 / October 14 / Room España 4
Ultra-Low Power Sensor Systems – The Fuel for Artificial Intelligence
There is an increasingly stronger interaction between microelectronics, applications, and new megatrends in our society: demographic changes (urbanization, health care), sustainability (resource and energy management) and digitalization (from miniaturization over the IoT towards ‘big data’). This talk will discuss the role of microelectronic sensor circuits and systems in solving critical issues related to those megatrends. After an introduction into those problems, I will show both examples for sensor and for circuit technologies enabling these applications. To have impact onto the society such electronic systems however are not good enough yet: sensor system data need evaluation in the application context to be useful to the society. In especially, if artificial intelligence shall support such usefulness this learning is a mandatory step for the usefulness. Finally, I will discuss simple artificial intelligence algorithms, as well as how to make use of them not only in the application context, but also to enhance the performance of sensor systems.
Ralf Brederlow started his career at Corporate Research of Infineon Technologies in 1999 working on security aspects of MCUs, and sensor systems for bio-medical applications. In 2006 he joined Texas Instrument in Freising, Germany, being responsible for the research and development of new circuits and technology for TI’s still industry leading ultra-low-energy MSP430 microcontrollers. In 2014 he started a branch of TI’s research department Kilby Labs in Freising working on sensing topics. In 2019 he was appointed to a full professorship for circuit design at the Technical University of Munich.
Ralf Brederlow holds 32 patents and has published 68 papers. In 2008 he has been General Chair of the IEDM, from 2013-14 chair of the ESSDERC/ESSCIRC steering committee, and in 2018 Technical Program Co-Chair of the ESSCIRC conference in Dresden. He is a co-reciepient of the 2019 VLSI Circuit Symposium Best Student Paper Award, and a Senior Member of IEEE.
Title: How Life of the Mixed-Signal Designers Became Better with FD-SOI, or Best Design Methods with FD-SOI CMOS Technology
Speaker: Andreia Cathelin
Affiliation: STMicroelectronics (STM)
10:00-10:45 / October 14 / Room España 5
How Life of the Mixed-Signal Designers Became Better with FD-SOI, or Best Design Methods with FD-SOI CMOS Technology
This presentation will first provide a short overview of the major analog and RF technology features of 28nm FDSOI technology. Then we will focus on the benefits of FD-SOI technology for analog/RF and mixed-signal circuits, first at device level and then illustrate with several design examples. A special focus will be done all through the presentation on the unique advantages brought by body biasing in FD-SOI and the resulting design techniques offering best in class state of the art performance. We will understand that FD-SOI Body bias enables seamless software defined transistors’ Vt.
Andreia Cathelin started electrical engineering at the Polytechnic Institute of Bucarest, Romania and graduated from ISEN Lille, France in 1994. In 1998 and 2013 respectively, she received PhD and “habilitation à diriger des recherches” (French highest academic degree) from the Université de Lille 1, France. Since 1998, she has been with STMicroelectronics (STM), Crolles, France, now Technology R&D Fellow. Her focus areas are in the design of advanced RF/mmW/THz and ultra-low-power circuits and systems. She is as well one of the pioneers of FD-SOI CMOS design.
Andreia has had numerous IEEE responsibilities since more than 15 years: at ISSCC, VLSI Symposium and ESSCIRC for TPC and Executive/Steering Committees respectively, and is an SSCS elected Adcom member. She will be the TPC chair of ESSCIRC2020 in Grenoble.
Title: Highly Efficient Broadband mm-Wave PA for 5G
Speaker: Donald Lie
Affiliation: Texas Tech University
10:00-10:45 / October 14 / Room Andalucía 1-2
Highly Efficient Broadband mm-Wave PA for 5G
I will survey broadband high-efficient power amplifiers (PA) design for millimeter-wave (mm-Wave) 5G applications. PA target design specs and trade-off considerations on POUT, linearity, power-added-efficiency (PAE), bandwidth, etc. across the 5G FR2 band (i.e., 24.25 to 52.6 GHz) will be discussed to support 5G NR modulated broadband signals with high peak-to-average-power-ratio (PAPR). These mm-Wave PAs are designed to cover broadband operations (say at both 28 and 37 GHz), with 3dB bandwidth over 15-20 GHz. These PAs are designed in advanced technologies in 40 nm GaN, 22/45 nm CMOS SOI, 65nm CMOS, and 90/130 nm SiGe BiCMOS processes. The prototype medium-power PAs reveal performance trade-offs depending on PA topologies (Doherty, differential, stacked), technologies (III-V vs. silicon), and matching network, with peak PAE > 20%. Using 5G NR wideband GHz modulated signals at 64/256 QAM, some PAs achieve good linearity with EVM < 5% at POUT > 10 dBm without predistortion.
Donald Y. C. Lie received his M.S. and Ph.D. in electrical engineering (minor in applied physics) from Caltech, Pasadena, in 1990 and 1995, respectively. He held technical and managerial positions at companies such as Rockwell International, Silicon-Wave (now Qualcomm), IBM, Microtune, and is currently the Keh-Shew Lu Regents Chair Professor in the Department of Electrical and Computer Engineering, Texas Tech University, and also an Adjunct Professor in the Department of Surgery, Texas Tech University Health Sciences Center. He was a Visiting Lecturer to the ECE Department, University of California, San Diego (UCSD) during 2002-2007 and co-supervised Ph.D. students. His and his students have won 16 Best Paper Awards and authored 220 peer-reviewed technical papers and book chapters and holds seven U.S. patents. He is a Fellow of IEEE. His research interests are: (1) power-efficient RF/Analog IC/SoC design; and (2) interdisciplinary/clinical research on medical electronics, biosensors, oncology, and AI-assisted medicine.
Title: Simplifying Deep Neural Networks via Look-up Tables and Product of Sums Matrix Factorizations
Speaker: Chai Wah Wu
Affiliation: IBM T. J. Watson research Center
Chai Wah Wu
10:00-10:45 / October 14 / Room Andalucía 3-4
Simplifying Deep Neural Networks via Look-up Tables and Product of Sums Matrix Factorizations
We study 2 approaches to simplify the implementation of deep neural networks. First we look at using Look Up Tables to remove the multiplication operations and obviate the need of a multiplier. We compare the different tradeoffs of this approach in terms of accuracy versus LUT size and the number of operations and show that similar performance can be obtained with a comparable memory footprint as a full precision dense deep neural network. Secondly we reduce the number of trainable model parameters by decomposing linear operators as a product of sums of simpler linear operators which generalizes recently proposed deep learning architectures such as CNN, KFC, Dilated CNN, etc. We show that good accuracy on MNIST and Fashion MNIST can be obtained using a relatively small number of trainable parameters. Furthermore, the generality of the framework allows it to be be suitable for general problems unlike CNN which performs best in the image processing or other shift-invariant domains.